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philips semiconductors data communications products applications note an4003 fiber optic receiver applications note 1 october 12, 1992 i. a new fiber optic receiver chip set for 100mb/s fddi da t a links ? SA5222 t ransimpedance amplifier . ? ne/sa5224 and ne/sa5225 post amplifiers figure 1. SA5222 low power t ransimpedance amplifier a1 a2 a3 a4 input 3 6 + 7 v out i in r f v out the 140mhz t ransimpedance amplifier (figure 1) designed specifically to meet the requirements of the ansi fiber distributed data interface (fddi) 100mb/s lan systems, the SA5222 is a new addition to philips semiconductors family of fiber optic devices. t able 1 shows a comparison of the features of this device in relation to the existing transimpedance amplifiers. particular attention has been paid to improving the power supply rejection ratio (psrr). this reduces the chance of oscillation due to coupling onto the supply line. the psrr specification, as noted in t able 1, is 57db. in addition the supply current is reduced to 9ma, a particular advantage in remote, high density applications. figure 2. SA5222 input stage (simplified) c m r m 150 w v i q 1 q 2 13k w pin 3 2.6v +5v r tr 2 table 1. differential transresistance bandwidth i n input max m a i cc psrr SA5222 16.6k w 140mhz 1.8pa/ hz 115 m a 9ma 57db ne5212 14k w 140mhz 2.5pa/ hz 120 m a 26ma 33db ne5211 28k w 180mhz 1.8pa/ hz 60 m a 24ma 32db ne5210 7k w 280mhz 3.5pa/ hz 240 m a 26ma 36db theory of operation SA5222 the SA5222 is an all-bipolar amplifier with a -3db bandwidth of 140mhz. the device operates in the inverting mode with the first stage loop closed by a shunt feedback resistance (see figure 2). the advantage in this topology is its inherent insensitivity to shunt capacitance at the input. the node at pin 3 of the amplifier acts to sum the input current from the photo or pin diode with the negative feedback from the shunt resistance. the input node is dominated by the miller feedback capacitance from the collector-base junction of q1 (c m ). this capacitance in conjunction with the miller resistance (r m = r in ), acts to set the upper frequency bandwidth of the amplifier. f 3db 1 2 r in c in the first stage miller capacitance is approximately 7pf and the miller resistance is equal to the rated input resistance of 150 w . the upper 3db bandwidth is then f 3db 1 2 150 7 10 12 f 150mhz which agrees with the device specifications. the virtual capacitance now dominates the frequency response of the amplifier desensitizing it to small values of input shunt capacitance. figure 3. SA5222 differential output stage (simplified) 1k w v i i b 1.9k w +5v 1.9k w v o 1k w 2ma 2ma the major advantage of this configuration over a cascade amplifier with fet input is that the input frequency response limit is stabilized and the noise gain is not drastically af fected by the external circuit capacitances. for example, with the rated 1pf package capacitance plus 1pf of external capacitance combined with 150 w , the input bandwidth is approximately 120mhz. this demonstrates the amplifier 's intolerance to shunt capacitance. adding external shunt
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 2 capacitance will lower the input stage bandwidth. this will also increase the noise gain, however . the shunt capacitance acts inversely with increasing frequency to increase the gain of the amplifier to internal noise currents. the input stage is followed by a dif ferential buf fer driver which provides the necessary interface and level shifting for the output emitter followers (see figure 3). the second stage converts the single-ended input signal to a dif ferential signal raised to a common mode voltage of 3.2v . the amplifier has a source/sink output capability of 2ma. the second stage provides a gain of slightly over two. npn current sources are bandgap referenced to provide highly stable biasing in the amplifier giving it an advantage in power supply rejection and linearity . the SA5222 dif ferential output resistance is typically 60 w and is, therefore, capable of driving low impedance circuitry . however, the output voltage of the SA5222 is 3.2v which limits the external dc load resistance to ground to a value which does not draw more than the rated 2ma of sink current. it is typically necessary to include capacitive coupling between the SA5222 and the post amplifier in order to allow the threshold comparators to automatically detect the bit amplitude and provide proper level conversion independent of preamp dc of fset. figure 4. ne/sa5224 postamplifier output disable using jam functions d out d out jam st st input amp ecl jam buffer sd buffer ref (4) (5) (15) (16) (10) (9) (8) (12) (13) data in v th d o d o st signal input v th lvl det (7) c f data out structure (typical) v cc 15 w 15 w r l r e v cc input sensitivity and signal-to- noise ratio example of optical conversion gain. consider a 10 m w optical signal incident upon a 0.45a/w att responsivity pin diode. this corresponds to 20db optical relative to 1mw (-20dbmo*). the current generated at the input node of the SA5222 is 4.5 m a. the resultant dif ferential output voltage is 4.5 a 16.6k 75mv p p between pins 6 and 7. the dynamic signal-to-noise ratio at this level is calculated below using the rated 1.8pa/ hz over a 150mhz bandwidth 20 log (75 10 3 ) v p p (1.8 10 12 ) 150 10 6 16.6k 47db whereas, a 1 m w (30dbmo) input into a typical 0.3a/w att responsivity photo diode or pin will result in a theoretical signal-to-noise ratio of 20 log 5 10 3 v p p (22 10 9 a rms ) 16.6k v rms 23db this does not include the optical noise of the fiber or the receiver diode. in this case the SA5222 output voltage due to the 1 m w optical input signal is 5mv p-p . (note: a 12:1 ratio or 21.6db corresponds to a ber of 10 9 .) *note: dbmo = dbm optical relative to 1mw . postamplifier selection (ne/sa5224 and 5225) in selecting the correct signal interface to meet user data communications system specifications, two dif ferent devices are available to the designer . for the fiber data distributed interface (fddi), the ne/sa5224 is recommended. this device provides 100k ecl compatibility for the dif ferential data output, status output and jam input. for industrial fiber communications applications, the ne/sa5225 is recommended. it provides 10k ecl compatibility . with the
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 3 exception of dif ferent hysteresis specifications, the two devices are fully pin-for-pin compatible. figure 5. +v cc q 1 220 w data in data in q 3 q 4 q 2 2ma v ee v o1 v o2 v t v t 2v t 2v t a. ne/sa5224, 5225 simplified input stage data input 0 b. ne/sa5224 input stage t ransfer functions 220 w 500 m a 500 m a 4.5k w 4.5k w v b v b 50mv theory of operation* referring to the operational block diagram in figure 4, the device consists of a main signal path that is fully dif ferential from input to output. the input amplifier consists of a dif ferential pair limited to an i cc of 2ma (see figure 5a). the amplifier is a limiting type with gain reduction above 2 v t , or about 100mv p-p . the input common mode voltage is approximately 2.9v with a v cc of 5v . the input resistance of the device is typically 4.5k w . this, then, allows the calculation of the minimum coupling capacitor for the lowest data frequency component. (see figure 5b.) the ne/sa5224 postamplifier the ne/sa5224 is designed to operate within the fddi specification data rate of 125mb/s using the 4b/5b format. at 100mb/s this requires the data clock to operate at 62.5mhz and presumes the use of an nrz format. the ne/sa5224 is rated to operate over a frequency range of 1khz to 120mhz, but will operate higher in frequency with some loss of sensitivity . the first stage input capacitance is on the order of 1.5pf including the esd diode junction capacitance plus the input device and package contributions. following the first stage are the intermediate gain stages from which a sample of the amplified signal is fed to the level detector . (*unless stated, also applies to ne/sa5225.) hysteresis v tl (off) v th (on) figure 6. level detector this section provides the programmable threshold function of the device. adjustment of the voltage on pin 16 determines the point at which the input signal decision level occurs. the threshold levels are rated for the single-ended voltage trip level of 2 to 12mv p-p which corresponds to twice this value or 4 to 24mv p-p differentially (see t able 2). threshold sensing may be combined with the output signal function through use of the data out jam functions). this allows you to force the output to a fixed state when the input falls below the predetermined level as programmed on pin 16. this function is provided by connecting pins 8 and 9 together . table 2. v set v tl v th v p-p(avg ) r 1 r 2 0.5v 3.6mv 6.4mv 5.0mv 4050 w 950 w 1.0v 7.2mv 12.8mv 10.0mv 3110 w 1890 w 1.5v 10.8mv 19.2mv 15.0mv 2160 w 2840 w 2.0v 14.4mv 26.0mv 20.0mv 1210 w 37900 w the signal level detector controls the status detector , which has complimentary outputs at pins 9 and 10. pin 9 is forced to a high state whenever the input to the ne/sa5224 falls below the user determined voltage threshold as set on pin 16 (v set ) (see figure 4). in the jam state, the ecl data outputs are forced into predetermined states, d out = low and d out = high. the complimentary st output at pin 10 may be used as a system status enable providing an ecl high when the input signal level is above the threshold level. the status circuit operates on the basis of a full wave rectifier averaging detector with a nominal response time of 1 m s. additional filtering may be added at pin 7, (c f pin) which has characteristic internal resistance of 24k w . this allows the user to select the time constant of the low-pass filter to meet a specific application by adding external capacitance at this pin. note that the capacitor is returned to the plus v cc line. the hysteresis characteristic of the ne/sa5224 is fixed internally between 4 and 6db. the plot in figure 6 shows how this relates to the threshold levels discussed above. the typical value in db is determined by taking 20 times the log of the ratio of v th (on) to v tl (of f) and for the ne/sa5224 this equals 5db. the ne/sa5225, however , has a typical hysteresis value of 3db with a tested range of 2 to 4db.
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 4 data in c1 c2 a1 + a3 a6 data out a4 d in d inb r in c az r az 250k w r az 250k w d out d outb 4.5k w r in 4.5k w v bias ecl 100k figure 7. ne/sa5224 forward gain path including auto-zero 100 w 10 m h 10 m h 10 m h 0.1 m f 0.1 m f bpf 31 j x2 1 3 2 4 5 6 7 8 ne5222 4 1 2 5 16 7 10 9 12 13 8 14 6 q1 q2 led status out +2v reference limiting amp ecl buffer +2v figure 8. 125mb/s fiber optic t est board for ground referenced ecl low signal detector 130 w 130 w 36 w 10k w 10k w 5 w 5 w 10 w st st + v out v cc2 v cc1 r tr v out gnd 2 gnd 1 0.1 m f 1k w 50 w 0.1 m f c az v r v set v cca i l ne/sa5224 analog ground digital ground 3.2v 3.2v +5v v cca 3.2v 10 m h 3 11 st st lim amp ecl buf postamplifier ecl out 750mv 0 d out d out c f r 1 r 2 the auto-zero loop the auto-zero circuit provides closed loop feedback inside the ne/sa5224 which cancels the of fset voltage of the forward signal path (figure 7). essentially , the auto-zero circuit acts to cancel bias errors at the comparator due to component of fsets and the data' s average dc bias. the circuit is capable of cancelling the of fset ef fect of long strings of zeros in transmission preventing a drift to a false output logic level. the c az capacitor is determined according to the relationship
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 5 figure 9. fiber optic-based point-to-point communication link transmitter i in v+ led led driver data receiver v+ pin diode transimpedance data (ecl) amplifier postamplifier link st atus clock recovery data retiming optical fiber data link SA5222 ne/sa5224/5225 f 3db 150 2 r az c az where r az is specified by the data sheet. for example if a 0.1uf capacitor is used for c az , and r az = 250k w . f 3db 150 2 250x10 3 1x10 7 farad 1khz the lowest data frequency component must be above the 3db frequency by an order of magnitude in order to reliably be reproduced at the ecl output. lower frequencies will be filtered out by the az loop. the customer is referred to an1443 for a more in-depth discussion of data rate response time versus the auto-zero function. setting the threshold level a user programmable signal level detector is provided in both the ne/sa5224 and 5225. this circuit allows you to inhibit input signals which are below the predefined level as desired to provide a high quality output ecl signal, free of baseband noise. setting the threshold is simply a matter of choosing a resistor divider ratio, r 1 :r 2 as shown in t able 2 above, which connects from v ref , pin 15 to v set , pin 16 (see figure 4). this provides the level detector with a threshold reference voltage. a scaled, rectified and filtered copy of the input signal is then compared to this threshold voltage. the programmable range is 424mv p-p at the input and is a function of v set /100, a value which represents the average of v thigh and v tlow . the actual threshold levels are: v tlow v set 139 where r 1 r 2 5k is constant v thigh v set 78 for example for v set = 1.2v, v tl = 8.6mv and v th = 15.4mv . t able 2 shows various combinations of r 1 and r 2 with corresponding values of v set and threshold voltages. v hyst = v th v tl threshold levels as low as 4mv p-p can be reliably set up for signal detection at the ne/sa5224,25 input. for suf ficiently high signal levels the threshold may be maintained at an elevated clipping plateau allowing good rejection of incoming baseband noise. (note: 4mv p-p corresponds to @ 33dbmo for an input pin diode conversion ef ficiency of 0.45a/w .) ii. a typical receiver test board with ecl output the circuit shown in figure 8 represents a simple printed circuit receiver capable of 100mb/s data processing from fiber . the input photo optic device is a philips bpf31 pin diode optimized for a wavelength of 850nm. the various waveforms (figures 1 118) show signal levels produced within the receiver , for dif ferent optical power and data rates. supply voltages have been set for 5v on the SA5222 and +2v ; 3.2v on the sa5224. this allows grounded 50 w loads to be used at the output of the receiver . the dif ferential output of the transimpedance preamplifier is ac coupled to the ne5224 postamplifier to prevent any dc bias of fset in the preamp from af fecting the threshold accuracy of the output stage. the coupling capacitors are made suf ficiently large (0.1 m f) in order to pass the lowest frequency data component.
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 6 the threshold voltage is set to 1.0v by r 1 and r 2 at pin 16 of the ne5224 postamplifier . as noted in t able 2 this sets the threshold level, vth, at 12.8mv p-p . this corresponds to an input current on pin 3 of the SA5222 of i in 12.8mv 16.6 x 10 3 0.75 a or p opt 0.75 10 6 a 0.45a w 1.7 w or 28dbmo, minimum. c|az| is 0.1 m f for a low frequency data limit of 1khz. the status detector allows visual output to determine when the input signal level is above the receiver threshold described above. the light is on when signal level is below threshold. (figure 8). the optical receiver board construction (figure 19) supply decoupling is obtained by splitting up the various parts of the receiver with 10 m h chokes combined with low inductance chip capacitors placed in close proximity to the ic supply pin and grounded to wide ground plane copper areas. observe that the top and bottom of the printed circuit board is covered with copper ground plane within which the circuit traces are embedded. in addition, the bottom and top planes are tied together with connecting pins (soldered carefully) and placed at numerous points around the board. in particular this must be done where critical ground returns such as ground 1 and 2 of the SA5222 are brought out of the smd device. a good rule is to place top to bottom ground plane pins every half inch in critical areas. the supply is isolated between the input preamplifier , SA5222 and the post amplifier , sa5224. ground traces are also separated into input stage (analog) and output stage (digital) grounds. this technique provides a more stable circuit, in addition to allowing ground referenced ecl signal into 50 w loads at the output. noise immunity level detection is set to automatically block reception when input signals fall below the threshold. if left disconnected the jam function is inactive. the ne/sa5224 (100k ecl output) and the ne/sa5225 (10k ecl output) easily provide suf ficient signal detection and level translation accuracy for 100mb/s signal reproduction. the signal-to-noise ratio is primarily determined by the receiver input stage so that equivalent input noise versus input signal current and signal bandwidth sets the limits on the signal-to-noise ratio of the combined receiver . the noise immunity of the receiver proper , including the pc board, is determined by how well the layout is done. ground plane construction of the signal preamplifier and post amplifier (with regard to rf technique) is required. no high level signal traces should be returned near the input sections in order to prevent feedback oscillation. the overall gain of preamplifier and post amplifier is in excess of 100db with very wide bandwidth. this makes physical as well as electrical layout critical but reasonable once the rules are understood. good bypassing of the v cc lines, a low inductance ground plane and high quality passive components are required. note that 1o of copper trace 1/16tho wide is equivalent to 15nh of inductance. wide traces on all v cc and ground bus connections are mandatory . the same applies to the pin diode signal traces at the input stage.
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 7 figure 10. ne/SA5222/5224 signal response w aveforms 10ns/div 15ns main pos main size remove wfm 3 r2 main measurements compare & reference max 925.0 mv min 105.0 mv peak-peak 740.0 mv width 26.53 ns trig'd 5ns/div 38.6ns 125mv 11.4ns led drive clock ne5224 da ta (50 w load) 26mhz output output 74f3040 led source figure 1 1. ne/SA5222/5224 ecl t est board w aveforms 5ns/div 12ns main pos main size remove wfm 3 r2 main measurements compare & reference max 930.0 mv min 105.0 mv peak-peak 745.0 mv width 7.171 ns trig'd pan/ zoom off 5ns/div 38.6ns 125mv 11.4ns led drive clock ne5224 da ta (50 w load) 70mhz output output 74f3040 led source
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 8 figure 12. ne/sa5225 signal response w aveforms 750mv trig'd 5ns/div 11.4ns 30.6ns 45% 700ns t ime holdoff t rig level remove wfm 3 r1 main measurements compare & reference max 935.0 mv min 150.0 mv peak-peak 785.0 mv width 6.759 ns led drive clock ne5225 da ta (50 w load) 75mhz output output 74f3040 led source 500mv /div
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 9 figure 13. ne/sa5224 differential output 3.500ns 18.65ns cursor 2 cursor 1 remove wfm 3 avg (r2) main t1= 3.500ns cursor paired dots trig'd 5ns/div 39.6ns 625mv 10.4ns transmit signal ne5224 da ta (50 w load) 66mhz output output t2= 18.65ns d t= 15.15ns 1/ d t= 66.01mhz type v1= 561.7mv v2= 568.8mv d v= 7.031mv 66mhz data rate 5.1 m w optical input (846nm laser source) figure 14. ne/SA5222/5224 ecl t est board w aveforms transmit signal ne5224 da ta (50 w load) output output 1.800ns 7.860ns cursor 2 cursor 1 remove wfm 3 avg (r2) main t1=1.000ns cursor paired dots 2ns/div 16.24ns 3.76ns t2= 7.860ns d t= 9.660ns 1/ d t=103.5mhz type v1= 828.0mv v2= 863.5mv d v= 35.47mv 625mv 103mhz data rate 5.14 m w optical input (846nm laser source) trig'd
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 10 figure 15. ne/SA5222/5224 ecl t est board w aveforms trig'd 625mv transmit signal ne5224 da ta (50 w load) 100mhz output output 4.200ns 14.06ns cursor 2 cursor 1 remove wfm 3 avg (r2) main t1= 4.200ns cursor paired dots 2ns/div 17.44ns 2.56ns t2= 14.06ns d t= 9.860ns 1/ d t=101.4mhz type v1= 810.4mv v2= 808.7mv d v= 1.719mv 100mhz data rate 4 m w optical input (846nm laser source) center trace is digitally averaged with n = 32. lower trace is not. figure 16. ne/SA5222/5224 ecl t est board w aveforms transmit signal ne5224 da ta (50 w load) output output 2.800ns 17.66ns cursor 2 cursor 1 remove wfm 3 avg (r2) main t1= 2.800ns cursor paired dots 2ns/div 17.44ns 2.56ns t2= 17.66ns d t= 20.46ns 1/ d t=48.88mhz type v1= 885.9mv v2= 746.2mv d v= 139.6mv 125mv 100mhz data rate 2 m w optical input (846nm laser source) center trace is digitally averaged with n = 32. lower trace is not. trig'd
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 11 figure 17. ne/SA5222/5224 ecl t est board w aveforms trig'd transmit signal ne5224 da ta (50 w load) output output 4.200ns 14.06ns cursor 2 cursor 1 remove wfm 3 avg (r2) main t1= 2.800ns cursor paired dots 2ns/div 17.44ns t2= 17.66ns d t= 20.46ns 1/ d t=48.88mhz type v1= 877.7mv v2= 704.7mv d v= 173.0mv 625mv 2.56ns 100mhz data rate 1 m w optical input (846nm laser source) center trace is digitally averaged with n = 32. lower trace is not. figure 18. ne/SA5222/5224 ecl t est board w aveforms trig'd transmit signal ne5224 da ta (50 w load) output output 500mv/div 1.75ns cursor 2 cursor 1 remove wfm 3 avg (r2) main t1= 18.00ns cursor paired dots 5ns/div 39.1ns t2= 8.150ns d t= 9.850ns 1/ d t=101.5mhz type v1= 220.0mv v2= 205.0mv d v= 15.00mv 750mv 10.9ns chan sel r1 100mhz direct coupled square w ave input 40db below 1.5v p-p
philips semiconductors data communications products applications note an4003 fiber optic receiver applications note october 12, 1992 12 figure 19. pc board layout top to bottom copper foil bonding of pc board edges.

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